1. Field of the Invention
The invention relates to an electrostatic discharge protection circuit, and more particularly to a gate coupled electrostatic discharge protection circuit which is formed with parasitic capacitors generated using a principle of gate couple, to ensure that parasitic bipolar junction transistors can be speedily turned on to protect a related high-voltage device from damages.
2. Description of the Prior Art
In semiconductor industry, electrostatic discharge (ESD) is always a main reason to cause damages on ICs during manufacturing. For example, under an environment with higher relative humidity (RH), there will be several hundred, even several thousand, voltages of electrostatic charges detected when a person walks through a rug. In an environment with lower relative humidity, electrostatic charges will reach more than ten thousand voltages. When the rug or person bringing high-voltage electrostatic charges contacts a chip, the electrostatic charges will be discharged toward the chip, causing irretrievable damages on the chip. To prevent chips from any damages caused by electrostatic charge discharge, various electrostatic discharge protection circuits have been developed. Typically, in the prior art, an on-chip electrostatic discharge protection circuit is designed between an internal circuit and each pad for protecting the internal circuit from damages.
Referring to FIG. 1, a structure of a conventional high-voltage electrostatic discharge protection circuit is shown. In the conventional high-voltage electrostatic discharge protection circuit, a high-voltage N-well region 12 and a high-voltage P-well region 14 adjacent to each other are formed in an N-type substrate 10. A PMOS transistor 16 is formed on the high-voltage N-well region 12. The PMOS transistor 16 has its gate 18 and source 20 electrically connected to a high voltage V.sub.DD, together and its drain electrically connected to an input/output pad (I/P PAD) 23.
The source 20 is constructed by a P.sup.+ -type region 24, a P-grad region 26 and a P-drift region 28. The P-grade region 26 is beneath and sounding the P.sup.+ -type region 24. The P-drift region 28 is adjacent to the P-grade region 26, partly under the gate 18. Similarly, the drain 22 is constructed by a P.sup.+ -type region 30, a P-grade region 32 and a P-drift region 34. The P-grade region 32 is beneath and surrounding the P.sup.+ -type region 30. The P-grade region 32 is beneath and surrounding the P.sup.+ -type region 30. The P-drift region 34 is adjacent to the P-grade region 32, partly under the gate 18. Furthermore, on the high-voltage N-type well region 12, there are an N.sup.+ -base connection region 38 electrically connected to the high voltage V.sub.DD and a first isolation region 36, wherein the source 20 and the N.sup.+ -base connection region 38 are adjacent to both sides of the first isolation region 36.
Similarly, an NMOS transistor 42 is formed on the high-voltage P-well region 14. The NMOS transistor 42 has its gate 44 and source 46 electrically connected to ground V.sub.SS, together and its drain 48 electrically connected to the input/output pad 23. The drain 48 is constructed by an N.sup.+ -type region 50, an N-grade region 52 and an N-drift region 54. The N-grade region 52 is beneath and surrounding the N.sup.+ -type region 50. The N-type drift region 54 is adjacent to the N-grade region 52, partly under the gate 42. The source 46 is constructed by an N.sup.+ -type region 56, an N-grade region 58 and an N-drift region 60. The N-grade region 58 is beneath and surrounding the N.sup.+ -type region 56. The drift region 60 is adjacent to the N-grade region 58, partly under the gate 44. Moreover, on the high-voltage P-well region 14, there are an P.sup.+ -base connection region 64 electrically connected to the ground V.sub.SS, wherein the source 46 and the P.sup.+ -base connection region 64 are adjacent to both sides of a second isolation region 62. Additionally, there is a third isolation region 40 is formed on the N-type substrate 10 and between the high-voltage N-well region 12 and the high-voltage P-well region 14. In other words, the drain 22 of the PMOS transistor 16 and the drain 48 of the NMOS transistor 42 are located on both sides of the third isolation region 40.
Due to the requirement of high-voltage process, the P-well region 14 is formed with high resistance. Consequently, two parasitic bipolar junction transistors 66, 68 shown in FIG. 1 have a higher breakdown voltage (BV). Meanwhile, as shown in FIG. 2, the gates of the PMOS transistor 16 and the NOMS transistor are electrically connected to V.sub.DD and V.sub.SS. As a result, it is uneasy to turn on the parasitic bipolar transistors 66 and 68 to release electrostatic charges in a short time.